PerfCount for RISC OS

V0.01 (20/6/2020): perfcount.zip (29,653 bytes). Source code included. Suitable for ARMv5+.

PerfCount is a module to provide easy acces to the performance counters that are present on most/all ARMv5+ CPUs.

Features

• Reporting of which events are available, using a common ID scheme to provide some consistency between different CPUs
• Support for multiple contexts, each measuring different events. Note: Currently, only one context can be active at a time.
• Automatic & manual multipass/multiplexing system to allow you to gather data for as many events as you want, bypassing the limits on how many events the CPU can track at once
• 64bit counter width to avoid overflow
• Optional per-context Wimp task association to pause/resume monitoring depending on whether a specific task is active (e.g. for system-wide profiling)
• Filtering by privileged & unprivileged CPU mode (if supported by the CPU)

History

• 0.01 - 20/6/2020
  
  • First release

Legal

Copyright (c) 2020, Jeffrey Lee
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